Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor(MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS device includes a bulk semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS device is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
As an alternative to forming a MOS device directly on a bulk semiconductor substrate, the MOS device can be formed on a strained-silicon layer. The process for forming strained-silicon involves depositing a layer of silicon germanium (SiGe) on the bulk semiconductor substrate. A thin layer of silicon is subsequently deposited on the SiGe layer. The distance between atoms in a SiGe crystal lattice is greater than the distance between atoms in an ordinary silicon crystal lattice. However, there is a natural tendency of atoms inside different types of crystals to align with one another where one crystal is formed on another crystal. As such, when a crystal lattice of silicon is formed on top of a layer of SiGe, the atoms in the silicon crystal lattice tend to stretch or “strain” to align with the atoms in the SiGe lattice. A resulting advantage of such a feature is that the strained silicon experiences less resistance to electron flow and produces gains of up to 80% in speed as compared to ordinary crystalline silicon.
MOS devices using a strained-silicon structure typically fall in one of two groups depending on the type of dopants used to form the source, drain and channel regions. The two groups are often referred to as n-channel and p-channel devices. The type of channel is identified based on the conductivity type of the channel which is developed under the transverse electric field. In an N-channel MOS (NMOS) device, for example, the conductivity of the channel under a transverse electric field is of the conductivity type associated with n-type impurities (e.g., arsenic or phosphorous). Conversely, the channel of a P-channel MOS (PMOS) device under the transverse electric field is associated with p-type impurities (e.g., boron).
One consideration when manufacturing NMOS and PMOS strained-silicon transistors is the beta ratio (i.e., N/P ratio, drive current ratio) of the transistors. A beta ratio of approximately 3.0 is commonly used to maintain cell stability. However, it has been found that in MOS devices based on SiGe, the drive current of the N-channel transistor increases with respect to the drive current of the P-channel transistor, such that the N-channel transistor runs hotter than the P-channel transistor. A desired drive current ratio between N-channel and P-channel transistors can therefore not be maintained. Accordingly, a need exists for an improved method of forming devices on a strained-silicon structure that allows for optimum performance by controlling the beta ratio or drive current ratio of the N-channel transistor with respect to the P-channel transistor.